A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2023)

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摘要
Logic rewriting is an effective but time-consuming technique to optimize the multilevel logic network by rewriting subnetworks of the input network with other logic equivalent structures. However, contemporary multithread rewriting algorithms either fail to parallelize the subprocedures of rewriting for individual nodes (intranode parallelism) or require locks to ensure the mutual exclusive among the scheduled nodes that are rewritten concurrently (internode parallelism), hence inevitably decreasing the degrees of parallelism and the scalability. This article proposes a novel GPU-based logic rewriting acceleration framework to address the mentioned issues in two phases. First, to exploit the intranode parallelism, we propose recursion-free algorithms that parallelize subprocedures of rewriting, which was hard to achieve due to the highly recursive nature of original rewriting algorithms. Second, to exploit the internode parallelism, we propose a work scheduler that can schedule mutually exclusive nodes and a GPU-friendly data structure that can support efficient concurrent operations. The new work scheduler and data structure allow simultaneously processing plenty of nodes without using locks. Experimental results show that our method can achieve on average $3.81\times $ speedup, compared to the state-of-the-art GPU-parallel method with the same quality of results.
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关键词
Parallel processing, Boolean functions, Logic gates, Graphics processing units, Instruction sets, Data structures, Schedules, And-inverter graph (AIG) rewriting, GPU acceleration, logic rewriting, logic synthesis
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