H²C-TM: A Hybrid High Coverage Test Method for Improving the Detection of HtD Faults in STT-MRAMs

This paper proposes a design-for-testability (DFT) scheme and a test method to improve the detection of hard-to-detect (HtD) faults of STT-MRAMs. The proposed DFT scheme considers HtD faults which are undefined state faults (USFs). These states do not always lead to incorrect functionality during the test process resulting in test escapes. The proposed DFT scheme, which can be deployed as a standalone technique, is called USFA-DFT (an undefined state fault-aware design-for-testability technique). In this scheme, the USF detection is achieved through using a weak write before reading the cell. The weak write overwrites defective cells, causing an incorrect read output, without flipping the content of defect-free cells. To avoid test escapes or yield loss (over-testing) caused by process variation (PV) effects, we make use of a post-silicon calibration scheme. Next, to improve the detectability of HtD faults in STT-MRAMs, we suggest a hybrid high coverage test method (called (HC)-C-2-TM) which enhances the previous method called LCHC-DFT (a low-cost high-coverage design-for-testability technique) by combining it with USFA-DFT. This test method improves the HtD fault detection, by applying the weak write (controlled by USFA-DFT) before the stressed read operation (controlled by LCHC-DFT). This hybrid approach has a negligible area overhead (3.18% for a 1 kbit array). The results for the performance evaluation of the (HC)-C-2-TM scheme show that for intra-cell and inter-cell defects, on average, the improvements of 14.4% and 11.3% of HtD fault coverage, compared to those of LCHC-DFT, are achieved. Also, for intra-cell and inter-cell defects, the proposed hybrid approach outperforms USFA-DFT by 49.8% and 49.3% respectively. Finally, in the presence of the process variation, the proposed test method guarantees a robust DFT with only a maximum deviation of 10% from the nominal value.