A 166F2/bit 0.0136%-Native-BER Physically Unclonable Function Based on Gate-Overhang-Shortened Transistor.

Physically unclonable function (PUF) has been rapidly developed as a lightweight and tamper-evident on-chip key generation module for a wide range of hardware-security-oriented applications [1] –[6]. Most traditional PUFs’ raw output bits, which are susceptible to the temporal noise and environmental voltage-temperature (VT) variations, need to be well-stabilized using temporal/spatial majority voting, burn-in and dark (unstable) bit masking, etc. [1] –[5], in order to alleviate the design overhead of the error correction codes (ECC) at the following stage. Among these stabilization techniques, dark (unstable) bit masking has been demonstrated to be more efficient [1] –[4]. However, constrained by the weak mismatch of regular MOSFETs, a high ratio of raw PUF bits (25%$\sim $67%) have to be discarded to achieve a bit error rate (BER) close to 0%, leading to inferior area efficiency of the bit-cell array [2] –[4]. A relatively low masking ratio of 3.64% is reported in [1] by linearly amplifying the presented hybrid PUF’s in-cell mismatch, unfortunately, at the expense of a huge bit-cell of 21675F ² (10.2$\cup$m× 3.4$\cup$m) using 40nm CMOS.In addition, non-MOSFET devices exhibiting larger mismatch have been exploited to improve the PUF’s reliability at the very first entropy source stage [5], [6].In [5], a metal-silicon-contact-based PUF is presented by designing the contact hole size smaller than the design rule of the adopted process, however, sufficient randomness cannot be guaranteed without adding a two-step XOR operation, which is intrinsically a kind of post-processing-based non-physical entropy. Another highly-reliable PUF with low native BER of 6x1$0^{-6}$ is reported based on the emerging resistive-random-access-memory (RRAM) devices configured to the high resistance state (HRS) [6], nevertheless, the necessity of post-CMOS processing steps dedicated to the RRAM devices makes the standard-CMOS-based low-cost implementation infeasible.