Low Power Sense Amplifier For A 64×32 Bit Sram Array For IOT Application

The primary objective of this work is to construct a sense amplifier that has a low power consumption and that can be further implemented in a 64x32 bit SRAM array by making use of a simulation tool developed by Cadence gpdk45 library (i.e. 45nm technology node). With the increasing demand of portable devices, sensing techniques are unavoidable part of memory system,Central Processing Units and for IOT (Internet of Things) applications, low power has become a very important parameter to be used in a efficient memory design. With the increase in CMOS scaling technology, transistor threshold voltage mismatch increased resulting in offset voltage in SRAM design. So a low power consuming and offset voltage compensating sense amplifier is proposed which has a reduced power delay product of 47.64 percent and after implementing it in a SRAM array the power consumption is measured to be 104. 9mW.