Power-Efficient Hardware Design of ECC Algorithm on High Performance FPGA

Data security and GC concepts are the two most promising areas with which the world is most concerned nowadays. As everyday technological progress is witnessed, hackers also develop new techniques for penetrating security. People are migrating toward GC since the power consumption is also a big problem. Using the Zynq 7000 FPGA, we have tried to optimize the total power dissipation (TPD) for the ECC algorithm in our proposed work. The implementation is implanted on VIVADO ISE. In the proposed work, the TPD for ECC design on Zynq 7000 is analyzed for various clock (clk) pulses. From the power calculation, it is observed that the TPD gets decreased as the time clk pulse increases.