Energy-Efficient circuits with improved diode free adiabatic logic design methodology

This paper demonstrates a detailed analysis of an unique improved diode-free adiabatic logic (IDFAL) circuit. The IDFAL is operated based on adiabatic switching principle. To indicate the circuit effectiveness, numerous analyses are carried out on different complementary metal oxide semiconductor (CMOS) technology nodes. Logic circuits, viz., NOT and NAND are analyzed and simulated using the traditional CMOS design style and some popular adiabatic logic design techniques: two-phase clocked adiabatic static CMOS logic (2PASCL), diode free adiabatic logic (DFAL), adiabatic dynamic CMOS logic (ADCL), two-phase adiabatic dynamic CMOS logic (2PADCL), quasi-static energy recovery logic (QSERL), and clocked CMOS adiabatic logic (CCAL). The results are compared with the proposed design (IDFAL) at various operating frequencies. The results revealed that the IDFAL inverter circuit has the least power delay product (PDP) among the reported adiabatic design methodologies and saves 91.59 % over the counter-part CMOS inverter at 16 nm high-performance predictive technologies (HP_PTM).