Hardware implementation of particle swarm optimization with chaotic fractional-order

Engineering optimization methods based on meta-heuristic algorithms are computationally demanding and might present complex implementation issues for embedded devices with high constraints. One of the interesting meta-heuristic methods frequently utilized to address diverse optimization issues in the real world is particle swarm optimization (PSO). However, the most challenging constraints in real applications; having an optimal execution time for an optimal solution, added to avoid premature convergence and stagnation in the local optima. In this study, we propose the hardware implementation of an improved particle swarm optimization algorithm by using the fractional order concept and chaos theory named CF-PSO. The concept is to substitute a chaotic sequence generator for the values of random variables and to use fractional calculus in the velocity and position expressions. We provide a hardware design of the enhanced PSO on Field Programmable Gate Array (FPGA) to obtain substantially quicker execution speeds than those attainable in software implementation. A Xilinx Virtex-7 Pro Development Kit is used to implement the hardware-improved PSO design and evaluate its performance. To start, we put the suggested architecture to the test using a benchmark of four functions to demonstrate the effectiveness of this hardware implementation. Secondly, we contrasted it with three other PSO variations: the conventional PSO, the PSO using fractional order velocity (F-V-PSO), and the PSO using fractional order velocity and position (F-VP-PSO). The experimental results show that the hardware implementation of F-VP-PSO is between 1.082 and 21.25 times faster. CF-PSO algorithm can be implemented in the Virtex7 VC707 evaluation platform by utilizing less than 2% of the slice 462 registers and 16% of the slice LUT (Look up Table) resources.