Functional Verification of a RISC-V Vector Accelerator

Editor’s notes: With the mounting interest in the public domain RISC-V instruction set architecture the complexity of verification on RISC-V CPUs is at the forefront. Every RISC-V implementation must ensure it fully complies with the programmer’s manual, independent of the purpose of the program or the application. This article describes a reusable and extendable UVM environment to check the correctness of the executed instructions with a high degree of precision. —Vivek Chickermane, Cadence