A Karnaugh Map Approximate Adder With Intrinsic Error Compensation

Approximate computing emerges as a new design paradigm to fill the gap between rigid design specifications and limited on-chip hardware resources. In this paper, an approximate Karnaugh Map-based Error Compensation Adder (KMECA) with intrinsic error compensation characteristics for loop accumulations is proposed for power and area savings while providing minimal computation errors. The proposed adder is based on a smart modification of the Karnaugh map to acquire zero mean error and generate an internal error compensation effect for loop accumulations. KMECA achieves the smallest Normalized Mean Error Distance (NMED) and Mean Square Error (MSE) in loop accumulation compared with the previously published approximate adders. An error model is also proposed to portray the error characteristics and explain the error compensation effect of KMECA.