9.1 D1: A 7nm ML Training Processor with Wave Clock Distribution

Tim C. Fischer,Anantha Kumar Nivarti,Raghuvir Ramachandran,Ram Bharti,Derek Carson,Anton Lawrendra,Vineet Mudgal,Vivek Santhosh,Sunil Shukla,Te-Chen Tsai

2023 IEEE International Solid- State Circuits Conference (ISSCC)（2023）

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摘要

D1 is the ML training processor in the DOJO exa-scale computer system [1], [2]. DOJO applications include training ML networks that run on the Tesla Full Self-Driving (FSD) computer in Tesla vehicles [3], [4]. D1 chip design goals were high performance, wide operating range, and scalable and modular construction featuring reduced design mismatch and high block-reuse.

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