A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS.

A transimpedance amplifier (TIA) is a critical building block that impacts the noise, bandwidth, and power consumption of intensity modulation and direct detection (IMDD) optical links used in data centers. CMOS TIAs using the shunt-feedback (SF) topology (Fig. 12.2.1) have recently been shown to achieve adequate noise and bandwidth performance to facilitate 100Gb/s receivers [1–4]. However, the SF- TIA suffers from debilitating tradeoffs between its noise and bandwidth, which make it fundamentally challenging to improve noise/bandwidth performance beyond what has already been achieved. An alternative that has the potential to overcome the fundamental shortcomings of the single-ended (SE) SF-TIA is a differential TIA. Recognizing that the SE-SF-TIA only uses the photo-current flowing out of one terminal of the photodiode (PD), a differential TIA seeks to double the signal current by using the current coming out of the PD's other terminal (Fig. 12.2.1). As the PD current also flows in the complementary branch, the signal increases by 6dB at the cost of a 3dB increase in noise, resulting in a theoretical 3dB increase in SNR. However, achieving this 3dB SNR improvement in practice is difficult. To understand the reasons behind it, consider the conventional differential TIA as shown in Fig. 12.2.1. It employs capacitively coupled signal paths to bring the PD current to the TIAs. Resistors $\mathrm{R}_{\mathrm{B}1}(\mathrm{R}_{\mathrm{B}2})$ are used to reverse bias the PD and need to be chosen such that the corner frequency $(\mathrm{F}_{\mathrm{c}})$ of the high-pass filter formed by $\mathrm{R}_{\mathrm{B}1}\cdot \mathrm{C}_{\mathrm{C}1}(\mathrm{R}_{\mathrm{B}2}\cdot \mathrm{C}_{\mathrm{C}2})$ is low enough to pass the low-frequency components of the PAM-4 data. However, the maximum value of $\mathrm{R}_{\mathrm{B}1}(\mathrm{R}_{\mathrm{B}2})$ is limited by the tolerable voltage drop caused by the average PD current. For example, even a $300\mu\mathrm{A}$ average current with $\mathrm{R}_{\mathrm{B}1}=\mathrm{R}_{\mathrm{B}2}=20\mathrm{k}\Omega$ would entail a 6V drop, which is prohibitively large in fine-line CMOS processes. In [5], the bias resistor was replaced by a regulator to alleviate the voltage headroom issue. But this approach is severely limited by the conflicting regulator output impedance $(\mathrm{R}_{\text{OUT}})$ requirements: achieving a low $\mathrm{F}_{\mathrm{c}}$ requires a large $\mathrm{R}_{\text{OUT}}$ ; achieving good line/load regulation and power supply rejection (PSR) mandates a low $\mathrm{R}_{\text{OUT}}$ Even if $\mathrm{R}_{\text{OUT}}$ is made as high as $20\mathrm{k}\Omega$ and $\mathrm{C}_{\mathrm{C}1}=\mathrm{C}_{\mathrm{C}2}=20\text{pF}$ , the high-pass corner would be nearly 400kHz, which is about an order of magnitude higher than what is needed for low baseline wander. Consequently, further increasing $\mathrm{C}_{\mathrm{C}1}/\mathrm{C}_{\mathrm{C}2}$ is the only viable option for lowering $\mathrm{F}_{\mathrm{c}}$ However, the top/bottom plate parasitic capacitors $\mathrm{C}_{\text{PT}}/\mathrm{C}_{\text{PB}}$ of the coupling capacitors severely degrade the TIA performance in two critical ways. First, they shunt the photocurrent, significantly reducing the signal current flowing into the TIA and lowering the effective transimpedance at high frequencies. Second, they add to the TIA input capacitance, reducing the TIA bandwidth and increasing its noise [6]. Because of these drawbacks, practical differential TIA performance is not superior to an SE-TIA.