A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.

This paper presents a 2 × VDD mixed-voltage digital output buffer where its slew rate (SR) is automatically adjusted based on PVT (process, voltage, and temperature) detection. The developed buffer is the first to be fabricated using TSMC 16-nm CMOS Logic FinFET Compact (Shrink) LL ELK Cu 1P13 M process. Since slew rate is one of the major required parameters in many interfacing protocols, it is really hard to meet if the mixed-voltage output buffer is needed in FinFET processes. The major reason is the low VDD in these advanced processes. However, our buffer's SR is improved by implementing low threshold voltage (Vth) type of device for always-on driving transistors in the Output Stage, thereby increasing the output current. Moreover, since FinFET devices were used in the buffer, the stability of the gate drives of the said driving transistors must be ensured so that noise interference will be avoided. Lastly, the buffer's Timing Shifters used non-overlapping signaling control directly implemented at the transistor level to eliminate the errors caused by delay variations. Based on silicon measurement results, at a load capacitance of 20 pF, the said circuit can be operated at a maximum data rate of 250 MHz for both supply voltages of 0.8 and 1.6 V (namely external VDD or VDDIO), respectively. When the SR auto-adjustment is activated, the SR improvement is at least 49.2% and 37.5% for 0.8 and 1.6 V, respectively.