A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor

A 430-MS/s 7-b asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a 40 f $F$ input sampling capacitor is presented. The proposed ADC reduces the input capacitance, which is the load of the input buffer amplifier, by separating the input sampling capacitor and the capacitor array for digital-to-analog converter (DAC). A nonbinary weighted capacitive DAC is used to relax settling requirement and the effect of reference fluctuations. The prototype ADC fabricated in a 28 nm FDSOI CMOS process occupies 0.00798 mm ² . Operating at 430-MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.5 dB and a spurious free dynamic range (SFDR) of 45.3 dB, at Nyquist. The power consumption is 2.52 mW at a 1.0 V supply voltage, resulting in a Walden figure of merit (FoM) of 107 fJ/conversionstep.