An FPGA-based readout chip emulator for the CMS ETL detector upgrade

L. Zhang, C. Edwards, D. Gong,X. Huang,J. Lee,C. Liu,T. Liu, J. Olsen,Q. Sun,J. Wu,J. Ye,W Zhang

arxiv（2023）

引用 0|浏览23

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摘要

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

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关键词

Digital electronic circuits,Front-end electronics for detector readout,Timing detectors

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