Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design

This paper presents a hardware-efficient Saturation-Aware Compressed Sensing (SA-CS) encoder design exploiting the saturation arithmetic based accumulator architecture. The SA-CS encoder can label saturated measurements when a low-bitwidth accumulator is employed, thereby enabling the adoption of the saturation rejection CS recovery algorithm for successful signal reconstruction. Both the optimal measurement bitwidth and the measurement compensation technique will be investigated with respect to the measurement saturation probability and the overall hardware cost. We implemented the proposed SA-CS encoder for ECG signal processing using the MIT-BIH Arrhythmia database. With a 13-bit measurement bitwidth, the proposed SA-CS encoder achieves 21.1% and 16.9% area and power savings as compared to a standard CS encoder design.