HPSW-CIM: A Novel ReRAM-Based Computingin-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation

Non-volatile memory (NVM) based computing-inmemory (CIM) systems can provide low-latency and highefficiency parallel multiply-accumulate (MAC) operations, which shows great potential in accelerating edge AI computing. In response to the limitations of miniaturization, parallelism, and low-power consumption of edge AI devices, this work proposes: 1. A hybrid-precision-signed-weight 1T1R (HPSW1T1R) sub-array realizes the signed-weight by constant-term resistor circuit without additional ReRAM array overhead. 2. A computing array reduces the IR-drop and transistor errors of the array by assembling a series of HPSW-1T1R sub-arrays and achieve high-density array integration. 3. Global-share ADCs (GS-ADCs) optimize the analog signals conversion process to improve computing parallelism. 4. Odd-Channel-Input- WeightInverse Coding (ORIWI) can further reduce IR drop by decreasing the accumulative SL current (ISL) inside the HPSW1T1R sub-array. In these manners, this work constructed a high computing-density HPSW-CIM calculation core for fully parallel MAC operation. The circuit-level evaluation shows that the energy cost of data conversion reduced by 2x-2.7x, reduces the peak column average current by 3.1x-6.2x, and improves array computing density by at least twice. The system-level evaluation shows that, in an HPSW-CIM core with 256KB memory in the 28nm process, the peak energy efficiency reaches 95.8TOPS/W@8bIN-4bW-8bO.