Common mode control loop for current mode logic-based circuits in FD-SOI technology.

Current mode logic (CML) circuits are widely used in digital, analog, and analog/mixed circuits due to their high-speed operation which makes them suitable for RF applications [1] and wireline transceivers [2]. CML amplifier shown in Fig. 1(a) has an output common-mode $(\mathrm{V}_{oCM})$ of where VDD is the supply voltage, I is the bias current and R is the load resistance. Supply voltage and load resistance in (1) are sensitive to PVT variations causing the common-mode voltage to change which may cause the preceding blocks to fail if they do not have a wide input common-mode range. One of the techniques to control the common mode is to apply current trimming by using multiple current mirrors, but this technique suffers from discrete control of each chip during testing. Another approach is to use a poly current reference generator [3] but this approach will require an extra block – reference generator – to be added as in [4] which uses not only a bandgap reference but also an adjust network to select the suitable bias for the CML blocks. Also in [5] instead of using any of the mentioned techniques, a CML to CMOS circuit is used to avoid the change in the output common mode voltage of the CML, but this circuit adds extra delay and power which can cause problems in some systems as in [1]