RISC-V based HW accelerator

2022 International Symposium on Electronics and Telecommunications (ISETC)（2022）

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摘要

This paper deals with implementation of an example of implementation of an algorithm into an FPGA. While some considerations about various possibilities (ASIC, ASIP, GPP) are made, here is demonstrated the ASIP version with implementation details. An economic version of a Reed-Solomon algorithm is demonstrated and further developments of the method are assessed.

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HW/SW codesign

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