A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver

With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/−6.55° tuning range with a step of 0.94°.