Parallel Single Parity Check Nodes for High-Throughput Fast-SSCL Polar Code Decoders

Successive-Cancellation List (SCL) decoding of Polar codes, supported by a Cyclic Redundancy Check, achieves a distinguished error-correction performance at the cost of a high decoding complexity. The parallel decoding of constituent Single Parity Check (SPC) nodes of a Polar factor tree relevantly contributes to the implementation costs of high-throughput, deeply pipelined SCL decoding architectures. In this paper, we present algorithms to reduce the number of considered candidates in SPC nodes. For this purpose, we adapt the partial order-based Rate-1 node candidate generation algorithm to the constraints in SPC nodes and deduce a low-complexity algorithm suitable for efficient hardware implementation. Simulation results show that the presented algorithms preserve the error-correction performance with reduced hardware implementation costs. Additionally, an extended threshold in the candidate selection enables a trade-off between error-correction and implementation costs by a further reduction of the considered candidates. Furthermore, Application-Specific Integrated Circuit (ASIC) implementations of the optimized node and three decoders with a code length of 128 in a 28 nm technology are presented. Regarding area efficiency and energy efficiency, improvements of up to 350.8 % and 84.7 % are achieved for the single SPC node with its sorter, while the presented SCL decoder implementations with list size 8 outperform a state-of-the-art reference decoder by up to 32.4 % and 32.0 %, respectively.