Latch-up Performance of a Sub-0.5 Micron Inter-Well Deep Trench Technology
Washington, DC, USA（1993）
Key words
CMOS integrated circuits,circuit analysis computing,digital simulation,integrated circuit technology,0.5 micron,3.3 V,60 mA,PISCES 2D simulations,enhanced current confinement,holding voltage,inter-well deep trench technology,latch-up performance,nonepitaxial bulk CMOS technology,sidewall inversion,sidewall leakage current,trench sidewall
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