Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET)

In this study, a negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET) with sidewall spacer engineering is proposed and its electrical characteristics are examined by technology computer-aided design (TCAD) simulation for lower subthreshold swing (SS) and higher on–off current ratio (Ion/Ioff) than conventional planar TFET. In detail, the dielectric constant (κ) and length of sidewall spacer (Lspc) which determine gate-to-source/drain underlap are optimized for an enhanced device performance. The simulation study shows that the sidewall spacers at source and drain underlap need to be designed differently for high Ion and low ambipolar current (Iamb). In case of source underlap, the HfO2 3 nm-Lspc can enhance outer fringing field and Ion. On the other hand, the SiO2 15 nm-Lspc at drain underlap can alleviate Iamb due to low outer fringing field. As a result, the asymmetric structure shows ∼ 1.5 times larger Ion and ∼ 4 orders lower Iamb with smaller SS and turn-on voltage (Von) than the conventional NCDG-TFET without sidewall spacer.