Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint.

H. Fukutome, K. Suh, W. Kim, Y. Moriyama,S. Kang, B. Eom,J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam,Y. Kim, S. Park, J. Park, H.-J. Cho, K. Rim, S. D. Kwon

Symposium on VLSI Technology (VLSI Technology)（2022）

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摘要

We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV ² ) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (V min ) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV ² . For the first time, we have demonstrated V min of 1-fin F/F same as 2-fin one and 27% CV ² reduction with keeping speed at a constant leakage.

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关键词

comprehensive feasibility study,single FIN transistors,switching energy,device footprint,standard cell height,minimum operation voltage,scaling switching energy,flip-flop

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