PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch.

P. Schuddinck, F. M. Bufler,Yang Xiang,A. Farokhnejad,Gioele Mirabelli, A. Vandooren,Bilal Chehab,A. Gupta,C. Roda Neve,Geert Hellings,Julien Ryckaert

Symposium on VLSI Technology (VLSI Technology)（2022）

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摘要

We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.

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关键词

PPAC,CFET,forksheet,scaling,SAGM,HOT

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