A Comprehensive Analysis in Recent Advances in 3D VLSI Floorplan Representations

Floorplan is one of the most critical steps of the physical design of VLSI Design flow. Decreasing size, interconnects, power consumption, and chip leakage are always on the top priority list for consumers and researchers. This article presents the latest advancements in one of the hot research topics in VLSI Physical Design: 3D Floorplanning. A lot of research articles have been studied for this article, and only major research points from some chosen relevant to 3D architecture articles have been incorporated in this paper. The 3D VLSI floorplan field is quite vast than the 2D VLSI floorplan and is comparatively less explored. This article reviews various aspects of floorplanning that cover floorplanning based on volume, tiers, vias, TSVs, and other representations of 3D VLSI Floorplan. These techniques, when applied as algorithms, help in simplifying the problem. These algorithms help optimize results that increase the chip’s overall performance. Some of the central representations have been incorporated in Sect. 5. Conclusion with research gap and future scope is described in the end.