A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector

This paper reports a 28-Gb/s bang-bang clock and data recovery (CDR) circuit based on the proposed phase detector (BBPD) including four sample flip-flops, two combined XORs, and a voltage-to-current converter. We employ a charge-steering technique to minimize power consumption, inserting one additional branch with a combined XOR into the proposed BBPD, to detect all code types. The CDR prototype pulls-off a 523.7-fs jitter performance with 13.8-mW power consumption.