Enhanced Candidate Selection Algorithm for Analog Circuit Verification
2022 International Semiconductor Conference (CAS)(2022)
摘要
In latest years, the complexity and applicability of modern Integrated Circuits (ICs) grew exponentially, hence the high-pressure to deliver IC designs faster on the market. For safety, a design meeting its specification under any allowed operating condition and fabrication variation is a prerequisite. Therefore, pre-Silicon (pre-Si) analog IC verification is an extremely important task, as in certain regions of this large parameter space, the device exhibits degraded performance, or it fails completely. During verification, a designer must find these regions of the input parameter space where the circuit fails. Ideally this must be done during pre-Si phase, to avoid potential huge re-design delays during prototyping or production. In this context, this paper presents a Machine Learning (ML) approach, where we sample the input space to offer good initial coverage of the operating conditions (OCs) hyperspace, with a small number of simulations. We denote one input of a circuit as an Operating Condition. We then leverage a ML-surrogate model of the circuit instead of time-consuming simulations to propose, during a candidate selection phase, new circuit worst cases, where the circuit fails. After updating the candidate proposal algorithm to include a Gradient Descent (GD) step, we highlight the performance improvement of this new method on synthetic circuits, where we obtain relative absolute verification errors below 1%, while using less simulations than other classical approaches.
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关键词
circuit verification,machine learning,process corners,surrogate models,analog circuits,formal verification
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