A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)(2022)
摘要
A 12-b pipeline ADC based on a new negative
$\boldsymbol{C}$
- assisted MDAC is presented. Proposed negative
$\boldsymbol{C}$
scheme aids to cancel gain error and nonlinearity by generating negative charges at the summing node during the amplification phase. A design strategy for ensuring stability even when the negative
$\boldsymbol{C}$
coexists is also introduced in this work. In addition, a highly
$\boldsymbol{G}_{\mathbf{m}}$
-linearized low-gain amplifier is proposed for negative
$\boldsymbol{C}$
implementation. The prototype ADC fabricated in a 28nm CMOS achieves 54.7dB SNDR and 71.8dB SFDR without any calibration at 320MS/s, demonstrating that the proposed scheme improves SFDR by +32dB across the Nyquist band.
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关键词
Analog-to-digital converter (ADC),multiplying digital-to-analog converter (MDAC),gain enhancement,negative capacitance,nonlinearity cancellation,pipeline ADC
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