An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking

2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)(2022)

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摘要
The RS(544,514) code with an error correction capacity of 15, also known as KP4 forward error code (FEC), has been adopted by IEEE Ethernet standards since it can make a good trade-off between complexity and decoding performance [1]. However, for high-speed (e.g., 800 Gb/s) Ethernet system, more powerful FEC codes would become necessary in order to achieve higher error correction ability than KP4 with a possibly minimal extra cost. In this paper, we introduce an RS-BCH concatenated FEC code to deal with this problem, where KP4 is used as the outer code and the BCH(144,136) code is as the inner code, both of which are carefully analyzed and selected. This concatenated code can not only achieve a better error correction performance, but also be compatible with the physical coding sublayer (PCS) of the latest Ethernet standard [2]. The software simulation demonstrates that the selected inner code is the optimal one under the currently widely-used interleaving scheme. Moreover, we propose a configurable high-throughput and low-latency RS-BCH decoder. The simulation and synthesis results show that our concatenated FEC code can achieve an extra coding gain (CG) of about 1.4dB at the bit error rate (BER) of about 1 × 10– 15 with a small overhead on hardware and power compared to the original KP4.
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关键词
Reed-Solomon (RS) codes,Bose-Chaudhuri-Hocquenghem (BCH) codes,concatenated codes,hardware implementation
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