Shared Round Core Architecture: A Novel AES Implementation for Implantable Cardiac Devices

The explosive growth of connectivity between IoT devices necessitates increased security measures to protect user data. Advanced Encryption Standard (AES) is one of the most popular and widely adopted symmetric encryption/decryption algorithms. The wide usage of AES (and other forms of encryption) in IoTs and other severely power constrained devices such as the implantable cardiac devices makes the low power implementation of AES critical. Traditionally, AES is performed with 128-bit data path, and frequently is aimed for high-speed processing. In this paper we introduce a novel ultra-low power global AES architecture, called Shared Round Core Architecture (SRCA), suitable for low frequency applications such as implantable cardiac devices. This architecture is obtained by reducing the data path from 128 to 32 bits and by merging the encryption and decryption data paths. Merging the data paths allows for the elimination of redundant calculation blocks and sharing of other blocks.