3DIC Stacking Process Investigation by Soldering Bonding Technology

Three-Dimension Integration Circuit (3DIC) is the key technology which widely applied in CMOS image sensor (CIS). AI and Could computing applications. Through 3DIC die stacking technology, it enables to reduce packageform factor. support higher I/O density and increase the data transimission bandwidth between memory and active die. However. the heterogeneous integration between different functional die which leads varius process challenges, such as wafer surface coplanarization treatment. small fine pitds and solder joint capability during the die bond (DB) process hence. in this paper. we sucessfully demonstrated 3DIC soldering bond technology in chip on wafer process by using 50 um thickness die In this 3DIC study, the different bonding technologies will he investigated in this paper, mass refits. (MR) and thermal compression bond (TCB) are studied in chip on wafer process. Tranditionally, mass reflow is the most efficiency and cost effective bonding technology, but the high tempature thermal cycling during the reflow process would lead serious warpage effect on substrate side, which causes the had bump joint quality such as non-wetting or bridge issue Therefore. TCB is an alternative solution to reduce the warpage effect of die bond process, the thermal is conducted from heater head to die directly. which decrease the thermal effect on substrate side so the good bump joint quality can be achieved by this bonding method. However. TCB has the features of lower throughput and higher cost than MR. these key factors should be considered in the mass production stage. In the tranditional reflow bonding technology. the Cu pillar bump pitch which smaller than 40um pitch is the challenge since the limited solder volume, by EDX mapping analysis. we observed the intermetallic compounds (IMG) void issue after mass reflow process due to the incompleted IMC formation. However, in this study, we successfully demonstrated 20 um ubump pitch in chip on wafer structure by optimizing the solder tip volume. In this study, 3DIC with thin die structure brings potential benefit to increase the vertical interconnected I/O density by shorten the ubump pitch and well solder joint quality by using mass reflow technology, Undoubtedly. the 3DIC structure is the mainstream for the AI, Could computing and memory stacking in the IC package industry, it brings much cost benefit and time to market advantage by select the suitable bonding technology of 3DIC structure.