Process Optimization by Virtual Target Design in Overlay Metrology

In modern DRAM processes, there are some critical layers that are particularly challenging for overlay (OVL) control. The conventional method of metrology target design for these challenging layers is to verify target performance using simulation based on the specific, final device process. After full simulations, target measurability issues can be encountered where the limited, available solutions (open hard mask, create topography, etc.) are costly and high risk. However, in DRAM new product R&D, there is always some tolerance for process tuning. The use of virtual Archer (TM) OVL measurements in metrology target design (MTD) can simulate metrology performance for these potential process splits, helping to find a good balance between process options and metrology performance. A significant improvement in target contrast for imaging-based overlay (IBO) is demonstrated by simulation on one of these challenging layers after process optimization as compared to the baseline (BSL) process. In this paper we will present the virtual MTD detailed flow and design considerations to achieve an optimized process and target design. The contrast of a key performance indicator (KPI) is improved by more than 30%, enabling OVL measurability of the challenging layer in new processes.