Parameterized FPGA Implementation of a Real-time Discrete Wavelet Transform Processor

This paper proposes and evaluates a parameterized Field Programmable Fate Array (FPGA) implementation of a Discrete Wavelet Transform (DWT) processor for streaming digital signal processing applications. Parameterization occurs during synthesis time and with respect to the number of decomposition levels and wavelet filters. Both parameters are taken into account to synthesize the group delay compensation module. The implementation of several wavelet families with varied number of decomposition levels and filter sizes was evaluated according to FPGA resource utilization and operating frequency. It was observed that the proposed architecture is resource constrained by the number of DSP blocks in the FPGA and time constrained by the routing delay of larger implementations. The system was tested operating at full analog-to-digital converter data rate (245.76 MHz) in a signal de-noising application.