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Enabling 3-Level High Aspect Ratio Supervias for 3nm Nodes and Below

D. Montero,V. Vega-Gonzalez,Y. Feurprier,O. Varela Pedreira,N. Oikawa,G.T. Martinez,D. Batuk,H. Puliyalil,J. Versluijs, H. Decoster,N. Bazzazian,N. Jourdan,K. Kumar,F. Lazzarino,G. Murdoch,S. Park,Z. Tokei

2022 IEEE International Interconnect Technology Conference (IITC)（2022）

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Key words
High-aspect ratio via,Supervia,BEOL,Ru,3nm node,scaling booster
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