A Novel NW-TFET Based Low Power, High Speed and Variations Resistant Comparator with Improved Linearity

This paper focuses on Hetero-Junction Nanowire TFET (HJ-NW-TFET) based circuit implementation. Here, a combination of an electrically doped drain, physically doped source and hetero materials form a HJ that provide better ON current and low ambipolarity in NW-TFET. Formerly, only device electrical characteristics are imported in circuit through Verilog-A modeling and least has been investigated regarding linearity and reliability. Whereas, physical variations incorporated during fabrication and environmental changes are two serious sources of design deviations which can neither be eliminated nor can be predicated as they are inherited and unique in nature. Therefore, to check the device performance in various situations a lookup table based low power comparator is implemented using HJ-NW-TFET. Comparator designed in this way has 10 ns delay even in low supply voltage and the effect of 10 % variations on HJ-NW-TFET performance is less than 5 % which promises distortion free and fault tolerant real circuit applications.