Gate Stress Study on SiN-Based SiC Power MOSFETs

Recently, high-k dielectrics attracted frequent research activities thanks to its potential to replace SiO 2 -based gate stacks in SiC power MOSFETs especially for voltage classes below 3.3kV. Here, the higher dielectric constants provide improved on-state performance due to significantly reduced specific channel resistances. Nonetheless, there are still white spots around understanding reliability issues and threshold voltage stability associated with gate stacks on SiC. This study investigates gate stress and burn-in effects of SiN-based gate dielectrics for 1.2kV SiC power MOSFETs. Particularly, we will shed light on the effects of gate stress on threshold voltage shift and bias temperature instabilities (BTI) of vertical SiO 2 /SiN power MOSFETs.