Diagnosis and Yield Learning

Yu Huang,Wu-Tung Cheng,Ruifeng Guo,Sameer Chillarige

2021 IEEE International Test Conference in Asia (ITC-Asia)（2021）

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摘要

With the advanced technology used in the semiconductor manufacture process, systematic defects related to layout patterns and litho process are the major cause of yield issues. In this industry session, we invite three experts from three EDA companies to share their experiences of diagnosis and yield learning.

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关键词

EDA,industry session,yield issues,litho process,layout patterns,systematic defects,semiconductor manufacture process,yield learning

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