Study and Optimization of Photo Resistor Etch Back Loop in HK Metal Gate

Photo resistor etch back (PREB) is an essential process in High-K Metal Gate, which can eliminate the height difference between nFET and pFET, and mitigate the pattern loading occurred in front end of line (FEOL). During PREB process, it is necessary to avoid SiGe damage, especially when photo resistor is being etched in etch back 1 (EB1) step. Moreover, the appearance of oxide residual and higher horn after PREB will ultimately lead to poly residue in dummy poly remove (DPR) process. In this study, those defects were studied systemically to illustrate their generation mechanism and adverse consequences. By suitable adjustment of photo resistor remain thickness, etch rate selectivity and etch amount, most of defects could be reduced or avoid to optimize PREB process.