The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

R. Ballabriga, J.A. Alozy, F.N. Bandi,G. Blaj,M. Campbell,P. Christodoulou, V. Coco, A. Dorda, S. Emiliani,K. Heijhoff, E. Heijne, T. Hofmann, J. Kaplon, A. Koukab, I. Kremastiotis, X. Llopart,M. Noy, A. Paterno,M. Piller, J.M. Sallesse, V. Sriskaran, L. Tlustos,M. van Beuzekom

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment（2022）

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摘要

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail.

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关键词

Hybrid pixel detectors,Sensor readout electronics,Precise timing,CMOS

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