Performance Analysis of Drain Pocket Hetero Gate Dielectric DG-TFET: Solution for Ambipolar Conduction and Enhanced Drive Current

In this brief, we explored the impact of drain pocket (DP) along with heterogenous gate dielectric (HD) on the performance of double gate tunnel field effect transistor (DGTFET). We investigated that an area and concentration optimized drain pocket, neighbouring drain region, has reduced ambipolar conduction to 7.2×10 -15 A/µm by deeply suppressing BTBT at the channel-DP junction. This decline is almost 8 decades down than conventional DGTFET. Also, the presence of Al 2 O 3 as a heterogeneous dielectric at the source side instigates charge formation and thus leads to steeper source-channel junction. Using Al 2 O 3 as HD has improved I ON to an order of 10 -5 A/µm together with abstaining rise in I OFF thus enhancing the I ON /I OFF ratio to an order of 10 11 as compared to the conventional counterpart. RF figure of merits has been analysed and appreciable improvement in g m and f T has been observed. All simulations have been carried out using 2-D Atlas device simulator. Simulation results submit that the proposed structure can overcome the challenges of TFET, and therefore it is suitable for low power analog as well as digital applications.