Response investigation of 3-stage 8 × 8 low-latency wideband TW-SOA switch for high-performance computing applications

High-performance computations (HPC) require switching structures to operate at high input powers with minimum latency and lower penalties. Keeping in view these challenges along with the restriction in existing modules and components, we present a response investigation of the proposed 3-stage 8 × 8 Wideband Travelling Wave Semiconductor Optical Amplifier (TW-SOA) based switch. The switch operation is better in terms of Bit Error Rate (BER) of e−13 to e−16, Extinction Ratio (ER) of 17.99794 dB, power penalty of 0.15–0.30 dB, and (Optical Signal-to-Noise Ratio) OSNR of 25.92411 dB. It is observed that increasing power per bit leads to interference of cross-port data that can be controlled by varying biasing conditions of SOA. A short response time of 0.61596 ns is achieved by utilizing small transient time values of cross-phase modulation occurring in SOA. To investigate the impairments that occurred during modulation of signal in TW-SOA loops by control signals, the switch performance is optimized for parameters at various input powers and injection currents to offer it an improved solution to switching challenges for HPC systems.