Green AI from Kirchhoff to Shannon

From the earliest beginnings, communications (theorized by Shannon) and computations (abstracted by Turing and von Neumann) have relied on schemes able to augment reliability. One was proposed by von Neumann and the other one was introduced by Moore and Shannon. For computations the gate-level method of von Neumann was embraced, while another one at the device-level was crafted by Moore and Shannon laying the foundation of network reliability. This device-level scheme was also intended for enhancing the reliability of computations, but was kind of sidetracked and ended up being employed for communications. Since then, steady advances towards single digit nanometer transistors have been constant. Lately, advanced technologies are in high demand for supporting the growing computational needs on which AI is blooming (as well as IoT and G5). As advance CMOS are sensitive to variations, it seems normal to analyze networks for identifying optimal ones, and the Moore and Shannon concept is a perfect fit for transistors/devices built and organized as arrays: FinFET, MBCFET, GAAFET, etc. Still, defining optimality in this context is a non-trivial task, as the conflicting power consumption and reliability requirements need to be analyzed and optimized simultaneously. For a better understanding we decided to start performing very detailed simulations of $$3\,\times\,3$$  resistor/transistor networks including variations (relying on the free ASAP7 PDK). We are reporting and discussing a few of those simulations here. Their statistical processing will reveal subtle and unexpected links between classical Kirchhoff theorems (pertinent for power consumption) and Moore and Shannon reliability concepts (theoretical). Plenty of additional investigations will be needed. Still, the main conclusion (based on the preliminary simulations we shall present) is that identifying optimal networks for low-power reliable CMOS designs (for computations) is a complex but doable task.