Low cost ic tester using pseudo-random approach

Lowcost IC testing is now a burning issue in semiconductor technology. Conventional IC tester, ATE (automatic test equipment), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo random testing approach has been emerged as an economically viable alternative to the expensive deterministic testing. This paper introduces a SOC implementing pseudo-random test technique for lowcost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-path facilities efficiently. It can also be used for testing PCB interconnection faults.