Logarithm-approximate floating-point multiplier

Approximate computing is a useful approach to save power and increase performance by trading Energy and accuracy. This paper proposes an efficient inexact floating-point (FP) multiplier using the idea of a semi-logarithm multiplier. In the proposed approximate FP multiplier, instead of the traditional mantissa multiplier, an approximate adder is used. The results show that the power consumption and delay of the proposed approximate FP multiplier have been decreased by 97% and 53% compared with the IEEE-754 single-precision exact FP multiplier. In addition, the proposed approximate FP multiplier provides an improvement of 81% in terms of area. Compared to the logarithm-approximate FP multiplier, the proposed inexact FP multiplier has 81%, 34%, and 34% savings in power, area, and delay parameters, respectively. High dynamic range (HDR) images are processed using the proposed approximate FP multiplier in smoothing and sharpening applications to show the quality of the proposed FP multiplier in image processing.