Warpage and Reliability Simulation of Super-Size Embedded Silicon Fan-out (eSiFO) Package with size 40mm×40mm

In 2017, Huatian developed silicon based fanout technology, named eSiFO, which used bare silicon wafer as carrier wafer. Compared with common fan-out technology based on molding compound, eSiFO has low warpage, low cost, better heat dissipation and easy to realize 3D integration with TSV technology. In order to meet the demand of multi-chip integration, a super-size eSiFO technology was reported in this paper. The packaging size is up to 40mm× 40mm, totally integrated four 14mm× 14mm. We studied the relationship between die thickness and warpage. Few samples were failed in temperature cycling reliability test. Finite element simulation were used to help failure analysis and some positive results were obtained.