RLDA: Valid test pattern identification by machine learning classification method for VLSI test

Testing of integrated circuits (ICs) is essential for weeding out defects before the products are shipped to customers. However, as circuitry shrinks in scale, the complexity of the circuit increases, leading to test cost increases. Considering test time (TT) taking too long due to pattern increases in digital circuits, a compact test set was selected to save TT without increasing test escape (when faulty circuits are undetected). Therefore, a machine learning (ML) classification method called regularized linear discriminant analysis (RLDA) algorithm was proposed. In this way, valid (test failed) patterns can be selected and invalid (test pass) patterns can be dropped to shorten TT. Results show that the least DPPM (97) for the same TT level, or the least TT (1.2s) for the same DPPM can be obtained.