Performance-driven Wire Sizing for Analog Integrated Circuits

ACM Transactions on Design Automation of Electronic Systems(2022)

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Abstract
Analog IC performance has a strong dependence on interconnect RC parasitics, which are significantly affected by wire sizes in recent technologies, where minimum-width wires have high resistance. However, performance-driven wire sizing for analog ICs has received very little research attention. In order to fill this void, we develop several techniques to facilitate an end-to-end automatic wire sizing approach. They include a circuit performance model based on customized graph neural network (GNN) and two optimization techniques: one using Bayesian optimization accelerated by the GNN model, and the other based on TensorFlow training. Experimental results show that our technique can achieve \(11\% \) circuit performance improvement or 8.7 × speedup compared to a conventional Bayesian optimization method.
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