Optimization of Photodiode Design through Analysis of Full-Well Capacity and Image Lag in 0.5 μm CMOS Image Sensors with Vertical Transfer Gates

Recently, the main issue for developing the latest small pixels is maintaining the full-well capacity (FWC) while minimizing image lag as the pixel pitch is scaled down within the sub-micron scale. In this letter, the FWC and image lag characteristics are optimized by varying the photodiode (PD) doping profiles in $0.5~\mu \text{m}$ CMOS image sensors with vertical transfer gates (VTGs) for the first time. Measurements and simulated results of various pitch generations are correlated to propose the most desirable PD doping conditions for $0.5~\mu \text{m}$ pixels which have not been developed yet. As a result, the ceiling position of the top PD doping significantly affects the image lag characteristics resulting in the lowest image lag when increasing the ceiling by 30% from the initial position. In conclusion, a fruitful guideline for photodiode design in 3D active pixel sensors is provided for optimization of FWC and image lag in $0.5~\mu \text{m}$ pixel pitches. Also, this methodology associating potential curve analysis can be of potential use for development in ultra-small pixel pitches in the near future.