基于FPGA的卷积神经网络并行加速设计

Computer Engineering and Design（2022）

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Abstract

为提升在资源、功耗受限的嵌入式平台上运行的深度卷积网络算法的速度和能效,提出一种基于现场可编程门阵列(FPGA)的卷积并行加速方案.利用卷积层与批归一化(batch normalization,BN)层融合减少计算复杂度;利用数据分片减少片上存储消耗;利用数据复用、并行计算提升运算速度,减少系统硬件开销;利用设计空间探索找到最符合硬件资源约束的计算并行度.实验结果表明,在100 MHz的工作频率下,加速器的峰值计算性能可以达到52.56 GFLOPS,性能是CPU的4.1倍,能耗仅为GPU的9.9％,与其它FPGA方案相比综合性能有一定的提升.

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Pretraining has recently greatly promoted the development of natural language processing (NLP)
We show that M6 outperforms the baselines in multimodal downstream tasks, and the large M6 with 10 parameters can reach a better performance
We propose a method called M6 that is able to process information of multiple modalities and perform both single-modal and cross-modal understanding and generation
The model is scaled to large model with 10 billion parameters with sophisticated deployment, and the 10 -parameter M6-large is the largest pretrained model in Chinese
Experimental results show that our proposed M6 outperforms the baseline in a number of downstream tasks concerning both single modality and multiple modalities We will continue the pretraining of extremely large models by increasing data to explore the limit of its performance

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