Low noise amplifier with adaptive gain setting - (AWAGS) ASIC

The ASIC design group at GSI developed an Amplifier With Adaptive Gain Setting (AWAGS) chip. The input stage based on a folded cascode architecture is followed by a single-ended to differential conversion and output buffers. To the contrary to usual ASIC designs, the capacitive feedback is divided into five capacitances with different values. Starting with the smallest one the capacitances are added to the feedback depending on the input charge. This concept allows to measure over a high dynamic range (>200000) with the highest precision in the individual gain setting. The AWAGS ASIC is produced in a UMC 180 nm UMC multi-project wafer (MPW) run 2020.